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Cadence is inviting application for the post of VLSI Physical Design
Location : Hyderabad
Position : VLSI Physical Design
Experience Senior level physical design engineers with 5-10 years of hands on design experience and have participated in at least 3-4 full chip tapeouts. Work experience covering multimillion gate SOC physical implementations from netlist to GDSII on 65nm and below technologies. 45nm/32nm/28nm technology experience preferred. Good proficiency in the following sub-areas covering: (expert level proficiency in 1-2 areas is highly advantageous) Floor-planning Budgeting Power delivery and IR analysis Clock tree synthesis Routing Optimization strategies Timing analysis and closure activities(including SI & MMMC) physical verification deep-sub micron effects 65nm and below including OCV, DFM, DFY etc. Experience with low power implementation methods and techniques would be helpful. Expert level user in at least one of: Cadence, Synopsys, Magma Physical Implementation Tools. Moderate to high levels of PERL, TCL, AWK scripting skills.
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